Conventionally, SRAM (Static Random Accesses Memory) and DRAM have been widely used as rewritable semiconductor memory devices.
SRAM uses static memory cells and a static memory cell usually consists of six transistors. Since static memory cells have driving capability and restoring capability, SRAM is mainly used for high-speed applications.
On the other hand, DRAM uses dynamic memory cells and a dynamic memory cell usually consists of one transistor and one capacitor. Since dynamic memory cells are small in size, DRAM is mainly used for applications that require large memory capacity. However, since dynamic memory cells have neither driving capability nor restoring capability, DRAMs need to perform refresh operations to read data and write the same data back within a specified refresh period in order to prevent memory loss due to leakage current and so forth.
In order to simplify the control of refresh operations, DRAMs having a self-refresh function have also been provided. DRAMs of this type have therein a refresh timer for measuring time against a predetermined time, and a refresh address counter for sequentially and internally generating addresses to be refreshed. DRAMs of this type enter into a self-refresh mode in response to an instruction supplied externally, and in that mode automatically perform refresh operations. Hence, it is an external memory controller that controls the refresh operations so that they may not compete with normal access operations.
In portable devices as represented by cell phones, SRAMs have been used in many cases since SRAMs can be easily used and the memory capacity required is not so large. In recent years, however, in order to support a utilization mode that requires a large amount of data, such as images, pseudo SRAMs have been increasingly used. Pseudo SRAMs are semiconductor memory devices, which use the same dynamic memory cells as those of DRAMs, and for which external interfaces and control methods from external devices are the same or almost the same as those of SRAMs, and Pseudo SRAM is referred to also as VSRAM (Virtual Static Random Accesses Memory).
Pseudo SRAMs require refresh operations, but in general they are constructed such that refresh instructions from external devices are not required. In this case, since refresh operations may possibly compete with normal read operations or write operations, refresh operations need to be controlled so that refresh operations may not prevent read instructions or write instructions sent from external devices. That is, pseudo SRAMs need to appropriately perform generation of a refresh activating signal and control of a refresh address counter, and so forth, which are required for internal refresh operations, while arbitrating the refresh operations with external accesses.
As one method of implementing such control, Japanese Unexamined Patent Publication (Kokai) No. 2003-187575 discloses a refresh control method of semiconductor memory device. According to this method, the number of occurrences of requests of starting refresh operations is monitored during the operation period of external access operations executed preferentially to refresh operations, and internal operations for refresh operations are controlled according to the number of occurrences. According to this method, refresh operations are prohibited during execution of external accesses. For this period, internal operations for the refresh operation for the first request of starting refresh operations are controlled, but internal operations for the second and subsequent requests for starting refresh operations is prohibited. Even if a plurality of requestsfor starting refresh operations are submitted while external access operations are being performed.
As another implementation method, Japanese Unexamined Patent Publication (Kokai) No. 2004-319053 discloses a semiconductor memory device in which long cycle limits can be relaxed. This semiconductor memory device is provided with a refresh controller for executing refresh operations. The refresh controller is provided with a refresh timing signal generating unit, a refresh request signal generating unit, and a refresh execution signal generating unit. The refresh request signal generating unit is provided with a first counter for counting the number of occurrences of the refresh timing signal, and a second counter for counting the number of occurrences of the refresh execution signal, and generates refresh request signal when the difference between two numbers of occurrences is one or more. When the difference is two or more, the refresh execution signal generating unit can generate the refresh execution signal two times or more during one cycle of the refresh timing signal.
In any of the aforementioned methods, the control is complicated, and thus the circuits are complicated. Moreover, in any of the methods, since operations are controlled only by arbitration between external accesses and internally generated refresh requests, refresh cannot be performed immediately when refresh becomes possible. For that reason, efficiency of refresh is low. This is a bar to maximizing efficiency of external accesses in applications in which data transmission speeds are maximized.